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4428E–8051–02/08
AT/TS80C31X2
Figure 14-2. Operating ICC Test Condition
Figure 14-3. ICC Test Condition, Idle Mode
Figure 14-4. ICC Test Condition, Power-Down Mode
EA
VCC
ICC
(NC)
CLOCK
SIGNAL
All other pins are disconnected.
RST
XTAL2
XTAL1
V
SS
V
CC
P0
Reset = Vss after a high pulse
during at least 24 clock cycles
RST
EA
XTAL2
XTAL1
V
SS
V
CC
V
CC
I
CC
(NC)
P0
V
CC
All other pins are disconnected.
CLOCK
SIGNAL
Reset = Vss after a high pulse
during at least 24 clock cycles
RST
EA
XTAL2
XTAL1
V
SS
V
CC
V
CC
I
CC
(NC)
P0
V
CC
All other pins are disconnected.
Reset = Vss after a high pulse
during at least 24 clock cycles
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